The UK Research Institute in Secure Hardware and Embedded Systems (RISE) will be holding a Research Showcase & Spring School at the Royal Academy of Engineering, London 5th – 6th March 2026.
The programme will cover two days, with a mix of keynotes, tutorials, presentations and interactive workshops, alongside updates on RISE Research and Impact Award projects.
Registration
Click here to Register Now and secure your place.
PhD & Researcher Bursaries
Please note that a limited number bursaries are available for UK-based PhD students and post-doctoral researchers, on a first come first serve basis. Bursaries can cover accommodation for up to 2 nights and travel costs. Requests for bursaries should be sent to info@ukrise.org after registering at the above link.
Agenda
| Day 1 Agenda – 5th March 2026 | |
|---|---|
| 09:00 – 10:00 | Registration – Tea / Coffee / Refreshments |
| 10:00 – 10:10 | Opening Remarks / Welcome (Professor Máire O’Neill, RISE Director) |
| 10:10 – 10:50 | Keynote: Simon Johnson, Intel Fellow & Confidential Compute Technical Director |
| Session 1: Hardware Security Primitives & Physical Unclonable Functions (PUFs) | |
| 10:50 – 11:10 | Secure-by-Design Photonic Identification Using Inhomogeneously Broadened Quantum Dot Physical Unclonable Functions (QD-PUFs) Dr Craig Allford, Cardiff University (Authors: Prof Peter Smowton, Cardiff University; Prof John Bowers, UC Santa Barbara) |
| 11:10 – 11:40 | Break & Networking |
| 11:40 – 12:00 | Synaptic-Inspired Security Primitive for Cryogenic Applications (SPICA) Dr Firman Simanjuntak, University of Southampton, Dr Wahyu Diyatmika, Von Ardenne GmBH |
| 12:00 – 12:20 | NeuroSecure – Building Trustworthy PUFs for Neuromorphic Chips Prof Merlyne De Souza, University of Sheffield, Dr Stefan Wiefels, Forschungszentrum Jülich |
| 12:20 – 12:40 | Chiral NanoGraphene for Multifield Semiconductor Security (ChiNGS) Dr Ashok Keerthi, University of Manchester, Prof Prince Ravat, University of Cologne |
| 12:40 – 13:00 | Multi-Parameter Physically Unclonable Functions with Thin-Film Multimodal Transistors (MULTI-TRUST) Dr Radu Sporea, University of Surrey, Dr Hans Kleemann, TU Dresden |
| 13:00 – 14:00 | Lunch & Networking |
| Session 2: Hardware Security Vulnerabilities & Mitigation | |
| 14:00 – 14:20 | Secure Start and Execution with Electronics Having Hardware Security Vulnerabilities Dr Amit Kumar Singh, University of Essex, Prof Prabhat Mishra, University of Florida |
| 14:20 – 14:40 | Side-Channel Analysis (SCA) and Countermeasure Implementation of Post-Quantum HQC on FPGA and ASIC Dr Anh Tuan Hoang, Queen’s University Belfast, Prof Samuel Pagliarini, Carnegie Mellon University |
| 14:40 – 15:00 | Foundations of Configurable Hardware Tracing for Monitoring Safety-Critical Systems Dr Martin Berger, University of Sussex |
| 15:00 – 15:20 | Hardware Root of Trust Reconsidered – Developing a Distributed Security Architecture to Protect Vulnerable Devices in the Semiconductor Supply Chain Dr Prosanta Gope, University of Sheffield, Dr Owen Millwood & Dr Witali Bartsch, Wiznet, Germany |
| 15:20 – 15:50 | Break & Networking |
| Session 3: RISE Impact Competition Winners | |
| 15:50 – 16:10 | SHIELD: A New Layer of Defense with Intelligent Hardware Monitoring for Safer Embedded Systems Dr Sangeet Saha, University of Essex |
| 16:10 – 16:30 | PaRtial Execution oF EncRypted dAta using reconfiguraBle hardware (PREFERABLE) Professor Gareth Howells, University of Essex |
| 16:30 – 16:50 | Combating fake media with edit-tolerant authentication Daniel Fentham, Professor Mark Ryan, Dr Xiao Yang, University of Birmingham |
| 16:50 – 17:00 | Day 1 Closing Remarks |
| 19:00 | Dinner: TBC |
| Day 2 Agenda – 6th March 2026 | |
|---|---|
| 09:00 – 09:30 | Registration – Tea / Coffee / Refreshments |
| 09:30 – 10:10 | Keynote: Design and Validation of RISC-V based Secure Microcontroller Chips Prof Georg Sigl, Director Institute for Applied and Integrated Security (AISEC), Fraunhofer |
| Session 4: Physical-Layer, Wireless & Optical Foundations for Secure Systems | |
| 10:10 – 10:30 | Securing Device Identification Using Hardware Impairments in RF Circuits Dr Junqing Zhang, University of Liverpool, Prof Aydin Sezgin, Ruhr-Universität Bochum |
| 10:30 – 11:00 | Break & Networking |
| 11:00 – 11:20 | Secure-by-Design Trust and Privacy via Hardware-Embedded Backscatter in Resource-Constrained IoT (SUBNET) Dr Xiaoqiang (Sean) Gu, University of Bristol, Prof Gregory D Durgin, Georgia Institute of Technology |
| 11:20 – 11:40 | Alliance on New Physical Layer-Based Ultra Secure Wireless Infrastructure (A-PLUS) Dr Aakash Bansal, Loughborough University |
| 11:40 – 12:00 | Security of Photonic Integrated Circuits Dr Cillian McPolin, Digital Catapult |
| 12:00 – 12:20 | Optical Sources for Secure Timing in Critical Infrastructures Dr Samuel Shutts, Cardiff University |
| 12:20 – 13:20 | Lunch & Networking |
| Session 5: AI & Hardware Security | |
| 13:20 – 13:40 | Establishing a Low-Cost Platform for Advanced Security Testing of AI Hardware Dr Chongyan Gu, Queen’s University Belfast, Dr Aydin Aysu, North Carolina State University |
| 13:40 – 14:00 | Security-Enhanced AI Inference Edge Processors Dr Amro Awad, University of Oxford, Prof Hussam Amrouch, Technical University of Munich |
| 14:00 – 14:20 | AI-Sec – Secure NoC Architectures for Deep Learning Systems Dr Arnab Biswas, Queen’s University Belfast, Prof Ankur Srivastava, University of Maryland |
| 14:20 – 14:50 | Break & Networking |
| Session 6: Assurance, Verification & Trust in the Semiconductor Lifecycle | |
| 14:50 – 15:10 | Security Assurance of Semiconductor Manufacturing (SASM) Dr Sridhar Adepu, Swansea University |
| 15:10 – 15:30 | Efficient and Correct Logic Equivalence Checking (ECLEC) Dr John Wickerson, Imperial College London, Prof Adam Chlipala, MIT |
| 15:30 | Closing Remarks |
This symposium is supported by the UK Department for Science, Innovation and Technology (DSIT).
Conference Chair
Prof Máire O’Neill, FREng
Regius Professor in Electronics and Computer Engineering, Director of the Research Institute in Secure Hardware & Embedded Systems (RISE), Queens University Belfast.
Your Speakers
Simon Johnson – Simon serves as the Strategic Lead for Confidential Computing in the Office of the CTO at Intel. The role covers Confidential Compute technical evangelism both internally and externally to the company, engaging with eco-system partners to deliver world class experiences and identifying and accelerating the next generation of hardware capabilities in the Confidential Computing space. Simon also serves as the SGX Program Architect.
Dr Craig Allford – Craig is a Research Fellow in Optoelectronics at the School of Physics & Astronomy, Cardiff University. He is currently employed by the EPSRC Future Compound Semiconductor Hub, whose vision is to establish the UK as the primary global research and manufacturing hub for Compound Semiconductor (CS) Technologies. The focus is on the advanced characterisation of laser diodes, and long-term degradation studies of these devices. This work allows us to understand how to improve both the performance, and operating lifetimes of III-V compound semiconductor laser diodes. For this activity we have established an extensive suite of characterisation tools and equipment.
Dr Sangeet Saha – Sangeet is a Lecturer (Assistant Professor) in the School of Computer Science and Electronic Engineering at the University of Essex. His research addresses key challenges in embedded systems, spanning real-time scheduling (FPGAs, multicore systems), fault tolerance, energy-efficient heterogeneous computing for edge AI, and embedded device cybersecurity. A notable outcome is the FORENSIC technology, funded by Innovate UK’s CyberASAP program and showcased at the National Cyber Security Centre’s (NCSC) flagship event, CYBER UK 2025. Dr. Saha’s research has attracted funding from NCSC, The Royal Society, Innovate UK (UKRI), and the Higher Education Innovation Fund (HEIF).
Prof Gareth Howells – Gareth is Professor of Cyber Security and Founder, Director and Chief Technology Officer of cyber security technology company, Metrarc Ltd, a University spin-out company. He has been involved in research relating to cybersecurity and secure communications for over 35 years and has published over 240 papers in the technical literature, co-editing two books and contributing to several other edited publications. His core research interests are device authentication, biometrics, secure communications and identity management. His principal contribution to cybersecurity is the development of ICMetric techniques for the derivation of digital signatures and encryption keys directly from properties of physical circuits. The technology significantly alleviates the need to store a copy of an encryption key and the work has given rise to several significant worldwide patents.
Prof Georg Sigl – Georg’s research covers hardware security, i.e. the design of secure circuits and embedded systems as well as the research on new hardware attacks. He finished his PhD in Electrical Engineering at Technical University of Munich in 1992. Afterwards he held several positions in research and development at Siemens and Infineon. From 2000 until 2010 he was responsible for the development of new secure microcontroller platforms in the Chip Card and Security division. Under his responsibility, two award-winning platforms have been designed. In June 2010, he founded the new chair for Security in Electrical Engineering and Information Technology at Technical University of Munich. In parallel, he is driving embedded security research as director at the Fraunhofer Research Institute for Applied and Integrated Security in Munich (AISEC).
Getting there
Prince Philip House
3 Carlton House Terrace
London
SW1Y 5DG
United Kingdom