q - RISE UK Research Institute in Secure Hardware and Embedded Systems

The UK Research Institute in Secure Hardware and Embedded Systems (RISE) aims to bring together the hardware security community in the UK to build a strong network of national and international research partnerships, accelerating the industrial uptake of research outputs and its translation into new products, services and business opportunities for the wider benefit of the UK economy. RISE is funded by the Engineering and Physical Sciences Research Council and the National Cyber Security Centre.

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Leaky Abstractions
Dr Alastair Reid – Senior Principal Engineer at Intel.

DPU Technology – Redefining next generation Datacenter Security
Prof Sakir Sezer – Queens University Belfast

Adaptive Trust Principles: the Foundation of Next Generation Vehicle
Shadi Razak – CTO at Angoka

Panel Session: Research to Reality
Louise Cushnahan, Shadi Razak, James Patrick Evans, Osney Capital

Protecting IoT in the Wild
Keith Graham – Head of University Program at Codasip

To Trusted Hardware (and back again?)
Hugo Vincent – Head of Security Group at Arm Research

Digital Security by Design, Challenge Update
Prof John Goodacre – Challenge Director at DSbD

A Deep Dive into FPGA Technology from a Security Perspective
Prof Dirk Koch, Heidelberg University

Practical and Formal Analysis Security of Contactless Mobile Payments
Dr Ioana Boureanu, University of Surrey

5G: Security from start to finish
Aaron Hogan - Engineering Director, Qualcomm

A Stab in the Dark: Blind attacks on the Linux Kernel
Professor Herbert Bos, VUSec Systems Security research group, Vrije Universiteit Amsterdam

IOSEC: Protection and Memory Safety for Input/Output Security

SCARV: A Side-Channel Hardened RISC-V Platform

User-controlled hardware security anchors: evaluation and designs

DeepSecurity:  Applying Deep Learning to Hardware Security

rFAS: Reconfigurable FPGA Accelerator Sandboxin

SafeBet-Memory capabilities to enable safe, aggressive speculation in processors

GUPT: A Hardware-Assisted Secure and Private Data Analytics Service

TimeTrust: Robust Timing via Hardware Roots of Trust and Non-standard Hardware, with Application to EMV Contactless Payments

Confidential Computing Tutorial
Ilhan Gurel, Ericsson

SCARV: A Side-Channel Hardened RISC-V Platform

IOSEC: Protection and Memory Safety for Input/Output Security

User-controlled hardware security anchors: evaluation and designs

DeepSecurity:  Applying Deep Learning to Hardware Security

SafeBet-Memory capabilities to enable safe, aggressive speculation in processors

TimeTrust: Robust Timing via Hardware Roots of Trust and Non-standard Hardware, with Application to EMV Contactless Payments

rFAS: Reconfigurable FPGA Accelerator Sandboxing

Mind the Gap: Promises, Pitfalls and Opportunities of Hardware-Assisted Security
Ahmad-Reza Sadeghi, TU Darmstadt

Hardware based Lightweight Authentication for IoT Applications
Gang Qu, University of Maryland

Perspectives on hardware security: embedding it everywhere, continuously and inexpensively
Massimo Alioto, National University of Singapore

PUF: From Research to Practice
Chongyan Gu, Queen’s University Belfast

Winning the War in Memory
Simon Moore, University of Cambridge

ARM's perspective on the importance of hardware security research
Richard Grisenthwait, ARM

CHERI - Architectural support for memory protection and compartmentalisation
Robert Watson, University of Cambridge

Accelerating Innovation
Louise Cushnahan, CSIT, Queen’s University Belfast

Why, Who, How and Where of Standards!
Charles Brookson, OBE

How to use Deep Learning for hardware security testing
Marc Witteman, Riscure

Software-based Microarchitectural Attacks
Dr Daniel Gruss, Graz University of Technology

Physical Attacks: Towards combined threat, protection and beyond
Shivam Bhasin, David Berend, Nanyang Technical University Singapore