RISE Projects

The RISE research challenges are being delivered through a series of projects. Currently we have three live projects, delivered through four Universities.

TruDetect: Trustworthy Deep-Learning based Hardware Trojan Detection

Prof Máire O’Neill | Dr Ihsen Alouani

The modern semiconductor supply chain uses overseas foundries, third-party IP and third-party test facilities. However, with so many different untrusted entities, this design and fabrication outsourcing has exposed silicon chips to a range of hardware-based security threats such as counterfeiting, IP piracy, reverse engineering and hardware Trojans (HT).

A hardware Trojan is a malicious modification of a circuit in order to control, modify, disable, monitor or affect the operation of the circuit. Although there have been no public reports of HTs detected in practice, in 2020, the cybersecurity company F-Secure published a report on their investigation into a pair of counterfeit Cisco Catalyst 2960-X series switches . While these devices did not have back-door functionality, they did employ measures to bypass processes that authenticate system components and F-Secure stated that motivated attackers use the same approach to insert hardware trojans to stealthily backdoor companies.

Such hardware threats are major security threats for safety-critical and embedded systems applications, e.g. in the medical, automotive or transport sectors. Due to the nature of this clandestine industry, it is very difficult to ascertain the true scale of the problem. However, in recent years both the sovereignty and cyber security of the semiconductor supply chain have become significant concerns for many countries.

The recently published EU Cyber Resilience Act (September 2022) outlines essential cybersecurity requirements for products with digital elements and states that such produced ‘shall be delivered without any known exploitable vulnerabilities’. In addition, the 2022 National Cyber Strategy 2022 outlines the need to ‘ensure that wherever possible the next generation of connected technologies are designed, developed and deployed with security and resilience in mind and embrace a ‘secure by design’ approach’.

The overall goal of the TruDetect project is to develop a trustworthy DL-based HT detection system that can be easily integrated into a security verification framework in EDA tools. This will include the design of novel countermeasures that ensure trustworthiness of the DL-based HT detection system against adversarial HTs and the use of Explainable AI to offer a comprehensive analysis of the DL system behaviour.

IOTEE: Securing and analysing trusted execution beyond the CPU

Prof David Oswald | Prof Mark Ryan

Dr Ahmad Atamli | Prof Vladi Sassone

Trusted Execution Environments (TEEs) allow users to run their software in a secure enclave while assuring the integrity and confidentiality of data and applications. However, cloud computing these days relies heavily on peripherals such as GPUs, NICs, and FPGAs. Extending the security guarantees of CPU TEEs to such accelerators is currently not possible. New technologies are being proposed to address this, notably the PCIe Trusted Device Interface Security Protocol (TDISP).

IOTEE is aims to evaluate the security guarantees of this new PCIe standard and its ability to provide trusted execution against strong adversaries. This will involve developing an emulator for the protocol, the use of formal modelling, as well as researching countermeasures against various software and hardware attacks.

SECCOM: Securing composable hardware platforms

Prof John Goodacre | Dr Bernardo Magri | Dr Lucas Cordeiro

This project seeks to identify and address the critical security issues arising from the creation of hardware platforms through the use of composable hardware systems.

Predominantly, current hardware architectures are statically defined and deliver therefore a predetermined level of security and properties by which its resilience can be verified.

In the simplest case, a static design supporting hardware extension, for example through a exported bus, such as PCIe, will deviate from the design’s initial security principles and will require mechanisms of encapsulation in its security model to constrain the indeterminable mechanisms by which extension of a system can perturb a static security model.

Although the provision of composable hardware may have understood security principles covering the creation of the resulting hardware platform, the arbitrary nature of composing the elements of a computer means that the resulting permutations lack any model of security by which threat models and mitigations can be evaluated.

The project proposes to conceptualise and evaluate across the design space of composable hardware platforms to discover whether key security properties and threat models can be extracted and used to create a security model from which the security of composed hardware can be validated. Further, given the dynamic nature of composed hardware, we will also investigate whether composed hardware can use dynamic verification mechanisms to assert security policy at runtime.

Beginning with platforms composed using PCI express switches in which the devices of a host can be shared and allocated dynamically between hosts, we will investigate the evolving and increased flexibility from Compute Express Link (CXL) and its ability to remove the host and device hierarchy while permitting any compute element to be a host or device while also providing shared access across the platform.

The objective outcome is to provide industry with a security model for a composed hardware platform from which security principles can be reasoned and demonstrated by its dynamic verification.

Previous Projects

Previous projects funded under RISE are listed below.

Projects funded under RISE 2017-2022:

SCARV: A Side-Channel Hardened RISC-V Platform
Dr Daniel Page

IOSEC: Protection and Memory Safety for Input/Output Security
Prof Robert Watson, Prof Simon Moore, Dr Theodore Markettos,

User-controlled hardware security anchors: evaluation and designs
Prof Mark Ryan, Prof Flavio Garcia, Prof David Oswald, Dr Eduard Marin

DeepSecurity:  Applying Deep Learning to Hardware Security
Prof Máire O’Neill

Projects funded under RISE 2018-2022:

SafeBet-Memory capabilities to enable safe, aggressive speculation in processors
Prof Simon Moore, Dr Jonathan Woodruff

GUPT: A Hardware-Assisted Secure and Private Data Analytics Service
Prof Pramod Bhatotia, Dr Markulf Kohlweiss

TimeTrust: Robust Timing via Hardware Roots of Trust and Non-standard Hardware, with Application to EMV Contactless Payments
Prof Ioana Boreanu, Dr Tom Chothia, Prof Liqun Chen

rFAS: Reconfigurable FPGA Accelerator Sandboxing
Prof Dirk Koch