Confidential Computing Tutorial, Ilhan Gurel, Ericsson
SCARV: A Side-Channel Hardened RISC-V Platform
IOSEC: Protection and Memory Safety for Input/Output Security
User-controlled hardware security anchors: evaluation and designs
DeepSecurity: Applying Deep Learning to Hardware Security
SafeBet-Memory capabilities to enable safe, aggressive speculation in processors
TimeTrust: Robust Timing via Hardware Roots of Trust and Non-standard Hardware, with Application to EMV Contactless Payments
rFAS: Reconfigurable FPGA Accelerator Sandboxing