The UK Research Institute in Secure Hardware and Embedded Systems (RISE) Annual Conference will be held at Prince Philip House, at the Royal Academy of Engineering, London on 6th November 2026.
Registration now open – Click here to secure your place!
Please note that we have a limited number of travel bursaries available for UK PhD students and early career researchers. Note that your research must be within the areas of hardware and embedded systems security. If your travel is more extensive, requiring a flight within the UK, we will also consider funding one night’s accommodation in London. Contact info@ukrise.org to find out more and secure your offer.
Conference Chair
Prof Máire O’Neill, FREng
Regius Professor in Electronics and Computer Engineering, Director of the Research Institute in Secure Hardware & Embedded Systems (RISE), Queens University Belfast.
Agenda
| RISE Annual Conference, 6th November 2026, Prince Philip House, London. | |
|---|---|
| 09:00 – 09:45 | Registration & Welcome Tea/Coffee/Refreshments |
| 09:45 – 10:00 | Opening Remarks/Welcome, Professor Máire O’Neill, Director, RISE |
| 10:00 – 10:45 | Keynote Session: Javier Orensaz Martinez, CEO, lowRISC (35 mins + 10 mins Q&A) |
| RISE Research & Impact Talks | |
| 10:45 – 11:05 | “BadRAM: Breaching Processor Security via Rogue Memory Modules” Professor David Oswald, Durham University, Professor Mark Ryan, University of Birmigham (15 mins + 5 mins Qs) |
| 11:05 – 11:25 | Break |
| 11:25 – 11:35 | Impact Competition introduction with Louise Cushnahan, Head of Innovation at RISE |
| 11:35 – 11:55 | “Securing Cloud Computing with Hardened Hypervisors” Dr Marius Muench, University of Birmingham (10 min pitch + 10 min feedback) |
| 11:55 – 12:15 | “SECCOM: CXL and QEMU- setup for research on composable systems” Dr Joshua Lant, University of Manchester (15 mins + 5 mins Qs) |
| 12:15 – 12:35 | “HARDAI” Dr Shancang Li, Cardiff University (10 min pitch + 10 min feedback) |
| 12:35 – 12:55 | “BlueGuard: Accelerated Host and Guest Introspection Using DPUs”” Dr Ahmad Atamli, University of Southampton (15 mins + 5 mins Qs) |
| 12:55 – 13:55 | Lunch & Networking (Poster Session) |
| 13:55 – 14:15 | TBC (15 mins + 5 mins Qs) |
| 14:15 – 14:55 | Early Career Academic and Researcher Pitches – 6 x talks, 5 mins per talk (40 mins total) |
| 14:55 – 15:10 | Break |
| 15:10 – 15:30 | “GridGuardian” Dr Mohammed Eissa, Sheffield University (10 min pitch + 10 min feedback) |
| 15:30 – 15:50 | “TruDetect: Trustworthy Deep-Learning based Hardware Trojan Detection” Dr Ihsen Alouani, Dr Niall McLaughlin, Queens University Belfast (15 mins + 5 mins Qs) |
| 15:50 | Closing Remarks |
| 16:00 – 16:45 | RISE ISAB Meeting (closed session) |
Our Speakers
Javier Orensanz Martinez
CEO, lowRISC
Javier Orensanz Martinez is CEO of lowRISC C.I.C., the Cambridge-based open silicon ecosystem organisation and home of the OpenTitan project. He was appointed CEO in June 2025, joining with more than two decades of experience in the semiconductor industry. He came to lowRISC after a 22-year career at Arm, including nine years in VP roles as General Manager of the Development Solutions Group, VP of Developer Ecosystems and VP of Quality, and is passionate about the commercial value of open source, having witnessed first-hand how it transformed Arm’s approach to software. At lowRISC he leads the organisation’s mission to create commercially relevant, open-source silicon designs that are widely adopted throughout industry.
Professor David Oswald
Durham University
David Oswald is Professor of Cyber Security in the Department of Computer Science at Durham University, having previously held academic positions at the University of Birmingham and Ruhr University Bochum. His main field of research is the security of embedded systems and trusted execution, with a focus on attack methods that exploit weaknesses in the physical implementation of cryptographic algorithms, including side-channel analysis, fault injection and reverse engineering. His work also spans the practical realisation of security in embedded applications and the analysis of trusted execution technologies such as Intel SGX and AMD SEV-SNP, as well as applications of CHERI as part of the Digital Security by Design initiative. He has published numerous papers at top-tier venues including TCHES, IEEE S&P, ACM CCS and USENIX Security, and was general chair of CARDIS 2022.
Louise Cushnahan
Head of Innovation, RISE/CSIT, Queen’s University Belfast
Louise Cushnahan is Head of Innovation at the Centre for Secure Information Technologies (CSIT), Queen’s University Belfast, which hosts the UK Research Institute in Secure Hardware and Embedded Systems (RISE), funded by EPSRC and the National Cyber Security Centre. She leads RISE’s commercial and innovation activities, including the RISE innovation and impact competitions that fund the translation of hardware security research into practical tools and technologies to solve real-world challenges. With a long track record of accelerating cybersecurity innovation, she previously managed CSIT Labs, an incubator programme for cybersecurity start-ups that has supported companies such as B-Secur, CyberLytic and Liopa, and works closely with industry, government and academic partners to drive commercial impact from UK hardware security research.
Dr Marius Muench
University of Birmingham
Marius Muench is an Assistant Professor at the University of Birmingham whose main research area is computer security, with a special focus on embedded systems, fuzzing, binary analysis and mobile network security. He obtained his PhD from Sorbonne University in cooperation with EURECOM and worked as a postdoctoral researcher at Vrije Universiteit Amsterdam before joining Birmingham. He developed avatar2, a framework for analysing embedded systems firmware, and FirmWire, an emulation and fuzzing platform for cellular basebands, and his research has led to the discovery and mitigation of vulnerabilities affecting millions of devices, from smartphone basebands to modern CPUs, microcontrollers and commercial cloud environments. He has presented his work at high-profile venues including Black Hat, DEF CON, REcon and Hardwear.io.
Dr Shancang Li
Cardiff University
Shancang Li is a Senior Lecturer (Associate Professor) in Cyber Security at Cardiff University, with previous affiliations at Swansea University, the University of Bristol and UWE Bristol. He also previously worked as a lecturer at Edinburgh Napier University and as a security researcher in the cryptography group at the University of Bristol, and has conducted mobile and digital forensics work across a range of industries and technologies, with a background spanning network penetration testing, wireless security, mobile security and digital forensics. His research interests include cyber security, digital forensics, privacy-preserving machine learning and secure computing, with recent work on IoT security, lightweight cryptography and privacy-enhancing technologies for the industrial Internet of Things.
Dr Ahmad Atamli
University of Southampton
Ahmad Atamli is a Lecturer in Cyber Security at the University of Southampton, where he leads hardware security research. He graduated with a BSc in Electrical and Computer Engineering from the Technion–Israel Institute of Technology in 2012 and received his DPhil in System Security from the University of Oxford in 2017, later joining Oxford as a Lecturer in Software Engineering before moving to Southampton. An ACM and IEEE professional member, he has published numerous papers and technical reports on IoT security, system security, hardware security, intrusion detection and malware analysis, and has established collaborations with national and international partners, including the H2020-funded ASSURED and TrustedFog projects.
Professor John Goodacre
University of Manchester / Challenge Director, Digital Security by Design
John Goodacre is Professor of Computer Architectures in the Department of Computer Science at the University of Manchester. previously Challenge Director for the UK Research and Innovation Digital Security by Design (DSbD) programme. He previously spent 17 years at Arm Ltd as Director of Technology and Systems, where he defined and introduced the first multicore processors, including the ARM MPCore, and other widely deployed technologies that enabled today’s smartphones and became the foundation for modern data centre infrastructure. As Director of DSbD, a £200M programme, he leads the effort to enable industry and researchers to create a step change in cybersecurity, blocking vulnerabilities by design and protecting operation and data by default. His research interests include new processing paradigms, web-scale servers, exascale-efficient systems and secure and ubiquitous computing.
Dr Joshua Lant
University of Manchester
Joshua Lant is a Research Associate in the Department of Computer Science at the University of Manchester. He has been a member of the Advanced Processor Technologies (APT) group since 2016 and was awarded his PhD in 2019 for work on FPGA interconnects in high-performance computing architectures. His primary research interests are in Linux networking and PCIe, FPGA interconnects and microarchitecture, and binary modification tools, and he works closely with Manchester’s contributions to the Digital Security by Design programme and its CHERI-based secure hardware platforms.
Dr Mohammad Eissa
University of Sheffield
Mohammad Eissa is a Lecturer in Digital Electronics in the School of Electrical and Electronic Engineering at the University of Sheffield. He earned a Bachelor’s degree in Computer Engineering followed by an MSc in Data Communication Engineering at Sheffield, before pursuing a PhD focused on translational digital engineering in chronic conditions. He has held several postdoctoral research associate roles in Sheffield’s Electronic and Electrical Engineering Department, researching novel statistical, machine learning and AI models and biomarkers, and has worked in digital healthcare technology with a mission to make it more inclusive and efficient, including close collaboration with the Royal College of Art combining design and technology to create user-friendly healthcare solutions. He is part of the School’s Semiconductor and Quantum Technologies research theme.
Getting there
Prince Philip House,
3 Carlton House Terrace
London
SW1Y 5DG
United Kingdom